MSI : Message Signaled Interrupt
The bus driver is responsible for initializing the message address and message data of the device function's MSI/MSI-X capability structure during device initial configuration.
An MSI capable device function indicates MSI support by implementing the MSI/MSI-X capability structure in its PCI capability list.
The MSI capability structure contains Message Control register, Message Address register and Message Data register.
Message Control Register : indicates the MSI capability supported by the device.
Message Address Register : specifies the target address
Message Data Register : specifies the characteristics of the message
To request service,
the device function writes the content of the Message Data Register to the target address.
the device and its software driver are prohibited from writing to these registers.
32 bit BUS 를 사용할 때는, lower 32bit MAR 을 사용
64 bit BUS 를 사용할 경우, upper 32bit MAR 을 사용
1. Bits 31-20 — These bits contain a fixed value for interrupt messages (0FEEH).
This value locates interrupts at the 1-MByte area with a base address of 4G – 18M.
All accesses to this region are directed as interrupt messages.
Care must to be taken to ensure that no other device claims the region as I/O space.
2. Destination ID — This field contains an 8-bit destination ID.
It identifies the message’s target processor(s).
The destination ID corresponds to bits 63:56 of the I/O APIC Redirection Table Entry
if the IOAPIC is used to dispatch the interrupt to the processor(s).
3. Redirection hint indication (RH) — This bit indicates whether the message should be directed to the processor
with the lowest interrupt priority among processors that can receive the interrupt.
• When RH is 0, the interrupt is directed to the processor listed in the Destination ID field.
• When RH is 1 and the physical destination mode is used, the Destination ID field must not be set to
0xFF; it must point to a processor that is present and enabled to receive the interrupt.
• When RH is 1 and the logical destination mode is active in a system using a flat addressing model,
the Destination ID field must be set so that bits set to 1 identify processors
that are present and enabled to receive the interrupt.
• If RH is set to 1 and the logical destination mode is active in a system using cluster addressing model,
then Destination ID field must not be set to 0xFF; the processors identified with this field must be
present and enabled to receive the interrupt.
4. Destination mode (DM) — This bit indicates whether the Destination ID field should be interpreted
as logical or physical APIC ID for delivery of the lowest priority interrupt.
If RH is 1 and DM is 0, the Destination ID field is in physical destination mode and only the processor
in the system that has the matching APIC ID is considered for delivery of that interrupt (this means no re-direction).
If RH is 1 and DM is 1, the Destination ID Field is interpreted as in logical destination mode
and the redirection is limited to only those processors that are part of the logical group of processors
based on the processor’s logical APIC ID and the Destination ID field in the message.
The logical group of processors consists of those identified by matching the 8-bit Destination ID
with the logical destination identified by the Destination Format Register and the Logical Destination Register in each local APIC.
The details are similar to those described in Section 10.6.2, “Determining IPI Destination.”
If RH is 0, then the DM bit is ignored and the message is sent ahead independent of whether the physical or logical destination mode is used.
Message Data Register
cf) The format of Message Data Register is same with ICR(Interrupt Command Register).
The related source code in KVM,
@ virt/kvm/irq_comm.c
static inline void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
struct kvm_lapic_irq *irq)
{
trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);
irq->dest_id = (e->msi.address_lo &
MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
irq->vector = (e->msi.data &
MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
irq->delivery_mode = e->msi.data & 0x700;
irq->level = 1;
irq->shorthand = 0;
/* TODO Deal with RH bit of MSI message address */
}