Relationship between H/W ring and S/W ring

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Relationship between H/W ring and S/W ring

I`m reading the ixgbe code especially about H/W ring and S/W ring. Is the relationship between H/W ring and S/W ring one-to-one mapping?
As far as I know, H/W ring size is determined in the code(hard coded) while S/W ring size is determined in port configuration time.
In the ixgbe_rx_alloc_bufs function, H/W ring header address and packet address indicate the DMA address of S/W ring's mbuf. I understand it means that the relationship between the H/W ring and S/W ring is one-to-one mapping. For example, if the size of H/W ring is greater than the size of  S/W ring then some portion of H/W ring is unused. Is it correct?

Thanks

Yes, there is a 1:1 mapping between the hardware and software ring entries, and both are sized depending on the configuration parameters passed to the ring setup APIs. As you state, the HW ring contains the DMA addresses of the packet buffers, while the sw_ring contains the pointers to the original mbufs. The two rings are always kept in sync in the code.