[ARM] NSACR (Non-secure Access Control Register)

Cortex-A9 에서 NSACR(Non-secure Access Control Register)는 Cortex-A9의 NEON MPE와 다른 시스템(SIMD)의 기능에 대한 접근 제어를 한다.

ㅇ RW register in Secure State

ㅇ RO register in Non-secure state

ㅇ only accessible in privileged mode 

Bits	Field	Function
[31:19]	-
[18]	NS_SMP	Determines if the SMP bit of the ACR register writable in NS mode 0 = A write to ACR in NS state takes undefined Instruction  exception and the SMP bit is write ignored 1 = A write to ACR in NS state can modify the vaule of the SMP bit
[17]	TL	Determines if lockable TLB entries can be allocted in NS state
[16]	PLE	Controls NS accesses to the Preload Engine resource,
[15]	NSASEDIS	Disable Non-secure Advance SIMD extension functionality
[14]	NSD32DIS	Disable Non-secure use of D16-D31 of the VFP register file
[13:12]	-
[11]	CP11	Permission to access coprocessor 11: b0 = Secure access only  b1 = Secure or Non-secure access
[10]	CP10	Permission to access coprocessor 10: b0 = Secure access only b1 = Secure or Non-secure access
[9:0]	-

참조 : 

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/CIHGCAFH.html (Cortex-A15)

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0409f/CIHGBGJA.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388h/CIHCHFCG.html