From DPDK-dev mailling list Relationship between H/W ring and S/W ring I`m reading the ixgbe code especially about H/W ring and S/W ring. Is the relationship between H/W ring and S/W ring one-to-one mapping? As far as I know, H/W ring size is determined in the code(hard coded) while S/W ring size is determined in port configuration time. In the ixgbe_rx_alloc_bufs function, H/W ring header addre..