Deep dive into Kernel

Cortex-A9 에서 NSACR(Non-secure Access Control Register)는 Cortex-A9의 NEON MPE와 다른 시스템(SIMD)의 기능에 대한 접근 제어를 한다. ㅇ RW register in Secure Stateㅇ RO register in Non-secure stateㅇ only accessible in privileged mode Bits Field Function [31:19] - [18]NS_SMP Determines if the SMP bit of the ACR register writable in NS mode0 = A write to ACR in NS state takes undefined Instruction exception and the SMP bit..

In this chapter, we can learn ARM's basic operation with registers. On the ARM processor there are 17 registers always available in any mode and 18 registers in a privileged mode. Each mode has a set of extra registers called banked registers. When mode is changed banked registers are swapped in 예를 들어, User mode일 때 r0~r15 까지는 범용 레지스터로 사용할 수 있다. 하지만 r13, r14, r15는 특별하게 취급되기도 한다. 따라서 일반적으로 r13~r15..

In an ARM processor, every interrupt is managed by GIC(Generic Interrupt Controller). The possible interrupt sources are (1)PPI, (2)SPI, and (3)SGI : PPI (Private Peripheral Interrupt) : Every processor have its own PPIs. SPI(Shared Peripheral Interrupt) : Every processor can access SPIs. SGI(Software Generated Interrupt) : This interrupt is generated by software writing to a GICD_SGIR register...